(i) Technical Field
A certain aspect of embodiments described herein is related to a method for fabricating a semiconductor device. Another aspect of embodiments described herein is related to a method for fabricating a semiconductor device including a nitride semiconductor layer.
(ii) Related Art
In a semiconductor device such as an FET (Field Effect Transistor), electrodes are formed on a semiconductor layer. In order to make it easy to flow a current between electrodes, it is required to form a low-resistance layer in a nitride semiconductor layer. The following paper describes an art of forming a low-resistance layer by implanting atoms in a semiconductor layer (Toshiyuki Oishi et. al., “High Performance GaN Transistors with Ion Implantation Doping”, Mitsubishi Denki Giho, August 2005, Feature Paper 07). Another paper discloses an art of etching a low-resistance layer to realize a desired interval between electrodes as well as the low-resistance layer (see J. S. Moon et. al., “55% PAE and High Power Ka-Band GaN HEMTs with Linearized Transconductance via n+GaN Source Contact Ledge”, IEEE ELECTRON DEVICE LETTERS, Vol. 29, No. 8, August 2008, pp. 834-837).
In order to prevent electrodes from being short-circuited, it is required to keep the electrodes spaced apart from each other at a given interval. However, the prior art may have an increase in the production cost of the semiconductor device and a difficulty in forming the low-resistance layer reliably.